module DECODE   (
        //      Inputs
        clk, rst, 
        addr_in, inst, reg_wr, reg_wr_data, reg_wr_addr,
        //      Outpus
        id_ex, addr_out, rd_data1, rd_data2, inst_pl,createdump,err
        );
        input   [15:0]  addr_in;
        input   [15:0]  inst;
        input           reg_wr;
        input   [15:0]  reg_wr_data;
        input   [2:0]   reg_wr_addr;
        input           clk;
        input           rst;

        output  [19:0]  id_ex;
        output  [15:0]  addr_out;
        output  [15:0]  rd_data1;
        output  [15:0]  rd_data2;
        output  [10:0]  inst_pl;
        output          createdump;
        output          err;
        /*      CTRL SIGNALS IN DECODE STAGE    */
        wire    [7:0]   ex;
        wire    [7:0]   mem;
        wire    [3:0]   wb;
        /*      PIPELINE REGISTERS : CONTROL SIGNAL      */
        dff     id_ex[19:0]
        (
                .q ( id_ex ),
                .d ( {ex, mem, wb} ),
                .clk ( clk ),
                .rst ( rst )
        );
        /*      PIPELINE REGISTERS : DATA PATH           */
        dff     addr[15:0]
        (
                .q ( addr_out ),
                .d ( addr_in ),
                .clk ( clk ),
                .rst ( rst )
        );
        dff     rd_data[31:0]
        (
                .q ( {rd_data1, rd_data2} ),
                .d ( {reg_rd_1, reg_rd_2} ),
                .clk ( clk ),
                .rst ( rst)
        );
        dff     ext_out[8:0]
        (
                .q ( wb_addr ),
                .d ( inst[10:2] ),
                .clk ( clk ),
                .rst ( rst )
        );
        /*      ID COMPONENTS           */
        rf      RF      
        (
                .read1data ( reg_rd_1 ),
                .read2data ( reg_rd_2),
                .err ( err ),
                .clk ( clk ),
                .rst ( rst ),
                .read1regsel ( inst[10:8] ),
                .read2regsel ( inst[7:5] ),
                .writeregsel ( reg_wr_addr ),
                .writedata ( reg_wr_data ), 
                .write ( reg_wr )   
        );

        ctr CONTROL 
        (
                .inst(inst[15:11]),
                .ext(ex[7:5]),
                .alusrc2(ex[4]),
                .aluop(ex[3:0]),
                .memrd(mem[7]),
                .memwr(mem[6]),
                .branch(mem[5:3]),
                .lbi(mem[2]),
                .j(mem[1]),
                .jr(mem[0]),
                .memtoreg(wb[3]),
                .regwr(wb[2]),
                .regdst(wb[1:0]),
                .createdump(createdump)
        );

